1. Technical Field
The present disclosure relates generally to semiconductor devices and their fabrication. In particular, the present disclosure relates to a strained ultra-thin silicon-on-insulator transistor formed by replacement gate.
2. Description of Related Art
Ongoing scaling efforts of semiconductor devices not only contribute to higher integrated circuit packing density, but also improve integrated circuit performance. As the scaling process proceeds towards the physical limits of currently available semiconductor technologies and techniques, newer technologies and techniques are developed to further decrease device size and increase device performance. As device size decreases, tremendous challenges arise in the areas of device modeling accuracy and process integration. The latest technologies for fabricating integrated circuits (or ICs) using “silicon-on-insulator” (or SOI) substrates have propelled semiconductor technology ahead for another generation or two of scaling. These SOI-based technologies accomplish this by balancing more expensive SOI wafer substrates with more advanced lithographic patterning tools and techniques. Integrated semiconductor devices based on thinner SOI substrates provide fully depleted transistor bodies, effectively eliminating undesirable floating body effects. Accordingly, there is a trend in the semiconductor industry towards ultra-thin semiconductor devices based upon ever-thinner SOI substrates. Another advantage of using ultra-thin SOI substrates is that they permit the body regions of semiconductor devices to experience a “strain” condition such that carrier mobility (both electrons and holes) is enhanced. The thinner the silicon layer of the SOI substrate, the greater the strain applied to it by the gate dielectric and buried oxide layer (BOX). In addition, ultra-thin SOI transistors have the advantages of improved short-channel effect, improved sub-threshold swing, and enhanced carrier mobility. It is one of the upfront approaches for continued complementary metal oxide semiconductor (CMOS) scaling. Another approach for CMOS scaling is strain engineering. One of widely adopted strain techniques is forming embedded SiGe (eSiGe) in the source/drain (S/D) of a PFET and embedded Si:C (eSi:C) in the source/drain of an NFET to produce a strain in the channel to enhance carrier mobility. Unfortunately, it is extremely difficult, if not impossible, to form eSiGe and/or eSi:C in ultra-thin SOI devices. eSiGe and eSi:C are formed by recessing a portion of the SOI in the source/drain region and then filling the recessed portion with SiGe for PFET and Si:C for NFET. Given the fact that the silicon layer is already very thin in ultra-thin SOI, it is very difficult to recess a portion of such thin SOI layer with a precise control. Furthermore, the strain is strongly dependent on the depth of the recessed S/D. Shallow recess in ultra-thin SOI results in very limited strain effect.
Therefore, there is a need for an improvement in forming embedded S/D in UTSOI.